Physical Design Lead, TPU, ASIC

• Lead the physical design implementation and strategy for high-performance silicon for critical, high-complexity subchips.
  
• Manage the full design cycle from RTL to GDSII, including critical sign-off closures for timing, electrical performance, and power integrity.
  
• Partner with internal teams (RTL, DFT, methodology, packaging) to achieve optimal power, performance, and area (PPA) results, including conducting feasibility studies for new microarchitectures and optimizing RTL runs.
  
• Collaborate with external EDA and IP vendors to improve flows and methodologies, while contributing to internal processes to ensure efficient and predictable execution.
  
• Drive execution schedules, resource planning, and risk mitigation for your area of ownership, scaling your leadership to support overall project-wide milestones.
  

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
  
• 10 years of experience in physical design, including leading full-chip or sub-chip implementation such as RTL2GDSII and overseeing key stages like floorplanning, place and route, and timing closure for high-speed ASICs across various process nodes.
  
• Experience in Python, Tcl, or Perl scripting.
  

Preferred qualifications:

• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
  
• Experience with Cadence Innovus, Synopsys DP, Mentor Calibre, and StarRC, and understanding of foundry technology files, rule decks, physical sign-off, and 2.5D/3D packaging.
• Technical leadership experience managing execution schedules, mitigating risks, and driving cross-functional collaboration with internal teams and external vendors.
  
• Understanding of performance, power, and area trade-offs, alongside knowledge of DFT including Scan, MBIST, and LBIST.
• Ability to navigate ambiguity, scale leadership across the physical design hierarchy, and excellent communication skills to articulate complex technical challenges to stakeholders.

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
  
• 10 years of experience in physical design, including leading full-chip or sub-chip implementation such as RTL2GDSII and overseeing key stages like floorplanning, place and route, and timing closure for high-speed ASICs across various process nodes.
  
• Experience in Python, Tcl, or Perl scripting.