Senior Machine Learning Engineer, AI Infra
New
We sent a six-digit code to . Enter it below — or use the link in the same email.
Or click the link in the same email — either works.
Enter the email address on your account and we'll send you a link to set a new password.
Remembered it? Sign In
You'll architect and implement complex digital blocks for AI connectivity silicon, owning designs from micro-architecture through silicon bring-up across PCIe Gen 6/7, CXL, UALink, and Ethernet protocols. This principal-level role requires 10+ years designing production SoCs in server, storage, or networking, with deep expertise in RTL implementation, timing closure, DFT, and advanced nodes below 7nm. You'll lead RTL development, collaborate across verification and physical design teams, and mentor junior engineers. The position is based in the United States and offers $185,000 to $230,000 annually depending on experience.
Written from this posting by Neural Jobs AI. The full description is below.
Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.
Principal Digital Design Engineer:
Role Overview
Join Astera Labs as a Principal Digital Design Engineer to architect and implement next-generation digital designs for high-performance AI connectivity solutions. You'll own complex blocks from micro-architecture through silicon bring-up, driving RTL implementation and collaborating with verification, physical design, and DFT teams to deliver production-quality silicon supporting PCIe Gen 6/7, CXL, UALink, UCI, Ethernet, and DDR4/DDR5 protocols.
This role offers the opportunity to work on cutting-edge technology at the forefront of AI infrastructure, taking ownership of critical design challenges in a fast-paced, collaborative environment where your contributions directly impact products deployed by the world's leading hyperscalers.
Key Responsibilities
Basic Qualifications
Preferred Qualifications
Salary range is $185,000 to $230,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits
We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.
Here is what this employer asked for. Sign in and we will fill in your half.
Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI.
209K – 275K
Our estimate — this employer did not publish a salaryOur estimate, not the employer’s. Worked out from the middle half of 29 comparable roles on Neural Jobs that did publish a salary, in the same field, country and experience band. The real figure for this job may be different.
Already have an account? Sign in
Continue without an account and apply on the Astera Labs website
Search by role, company, or anything a posting mentions.