Senior CPU Physical Design Engineer

• Partner with architecture, RTL, and DFT teams to optimize Power, Performance, and Area trade-offs.
• Own block and IP-level physical design implementation from synthesis through Place and Route.
• Debug critical timing paths and apply advanced physical design techniques to solve timing challenges.
• Execute signoff activities, including Static Timing Analysis, power recovery, and electrical layout checks.

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
  
• 8 years of experience with high-speed digital design, implementation, and Power, Performance, and Area (PPA) optimization.
• Experience with sign-off convergence domains, including Static Timing Analysis (STA), electrical checks, or physical verification.

Preferred qualifications:

• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
  
• Experience with advanced process nodes (e.g., 5nm, 3nm, 2nm, or below).
• Experience applying AI/ML-assisted techniques for physical design closure and PPA scaling.
• Proficiency in scripting (Python, Tcl, Perl) and data mining for QoR metrics.
• Understanding of EMIR flows, power grid design, and design reliability for high-frequency circuits.

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
  
• 8 years of experience with high-speed digital design, implementation, and Power, Performance, and Area (PPA) optimization.
• Experience with sign-off convergence domains, including Static Timing Analysis (STA), electrical checks, or physical verification.