Silicon Design Manager, RTL Machine Learning, Accelerator Design

• Lead, mentor, and manage a team of RTL Design Engineers performing tasks related to IP development for Compute Cores.
• Provide technical leadership to engineers and model best design practices (i.e., micro-architecture specifications, design reviews, code reviews, design methodology, etc.).
• Serve as the primary point of contact for all design-related activities on projects. Participate with Architecture and System Design teams in architecture definition, IP area estimation, power optimization, and performance enhancements.
• Collaborate closely with cross-functional teams (e.g., Verification, Design for Test, Physical Design, and Software) to make design plans and present project status throughout the development cycle.
• Drive improvements in design methodologies, processes, and quality control measures.

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
  
• 10 years of experience with Chip Design, ASIC Digital Design, and SystemVerilog.
• 8 years of experience in Computer Architecture and Register-Transfer Level.
• 3 years of experience in people management and developing employees.

Preferred qualifications:

• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
  
• Knowledge of high performance and low-power design techniques.
• Knowledge of ASIC Verification, Design For Testing (DFT), Synthesis, Static Timing Analysis (STA), or Physical Design.

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
  
• 10 years of experience with Chip Design, ASIC Digital Design, and SystemVerilog.
• 8 years of experience in Computer Architecture and Register-Transfer Level.
• 3 years of experience in people management and developing employees.