SoC and IP Design Engineer, Google Cloud

• Define the block-level design document (e.g., interface protocol, block diagram, transaction flow, pipeline, etc.).
• Perform Register-Transfer Level (RTL) coding (coding and debug in Verilog, SystemVerilog), function/performance simulation debug, and Lint/CDC/FV/UPF checks.
• Participate in synthesis, timing/power closure activities.
• Participate in test plan and coverage analysis of the block and SoC-level verification.
• Communicate and work with multi-disciplined and multi-site teams.

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
  
• 4 years of experience with digital logic design principles, RTL design concepts, and languages, such as Verilog or SystemVerilog.
• Experience with logic synthesis techniques to optimize RTL code, performance and power, as well as low-power design techniques.
• Experience with design sign-off and quality tools (e.g., Lint , CDC , etc.).
• Experience with SoC or IP architecture.
  
  

Preferred qualifications:

• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
  
• Knowledge of high-performance and low-power design techniques, assertion-based formal verification, Field-programmable Gate Array (FPGA) and emulation platforms, and SoC architecture.
• Knowledge in one of the following areas such as Double Data Rate (DDR)/Low Power Double Data Rate (LPDDR), High-bandwidth memory (HBM).
• Excellent problem-solving and debugging skills.
  
  

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
  
• 4 years of experience with digital logic design principles, RTL design concepts, and languages, such as Verilog or SystemVerilog.
• Experience with logic synthesis techniques to optimize RTL code, performance and power, as well as low-power design techniques.
• Experience with design sign-off and quality tools (e.g., Lint , CDC , etc.).
• Experience with SoC or IP architecture.