TPU PCIe Design Lead

• Lead the PCIe microarchitecture and Register-Transfer Level (RTL) development, ensuring high-performance designs that strictly adhere to Power, Performance, and Area (PPA) targets, coding standards, and quality guidelines.
• Manage the full RTL life-cycle, including documentation and coding, while ensuring the design is sign-off ready for Lint, CDC, and synthesis.
• Partner with system architects to integrate the PCIe subsystem, ensuring it meets chip-level bandwidth, latency, and power consumption goals.
• Coordinate with Verification and Physical Design teams to develop test plans, leverage PCIe VIP, and achieve successful timing closure.
• Resolve complex protocol issues and lead post-silicon bring-up to ensure link integrity and subsystem performance.

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• 10 years of experience in ASIC design, including one project focused on PCIe logic.
• Experience debugging RTL using Verdi/VCS and automating tasks via Python or Perl.
• Experience in SystemVerilog/Verilog for RTL development and microarchitecture definition.
• Experience with PCIe protocol layers (e.g., Transaction, Data Link, and Physical) or LTSSM.
• Experience with Clock Domain Crossing (CDC), timing closure, or synthesis flows.

Preferred qualifications:

• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
• 10 years of ASIC design experience, including 3 years in PCIe (Gen4/5/6) controller or protocol logic.
• Experience with advanced RTL design, including multi-clock domains, timing closure, datapath optimization, and hardware/firmware partitioning.
• Experience with cross-functional leadership, driving efforts with software/system teams from RTL development through silicon bring-up.
• Experience in PCIe architecture, including Link Training and Status State Machine (LTSSM), TLP/FLIT pipelines, flow control, ordering rules, and performance tuning.
• Knowledge of ASIC flow, SerDes, and scripting.

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• 10 years of experience in ASIC design, including one project focused on PCIe logic.
• Experience debugging RTL using Verdi/VCS and automating tasks via Python or Perl.
• Experience in SystemVerilog/Verilog for RTL development and microarchitecture definition.
• Experience with PCIe protocol layers (e.g., Transaction, Data Link, and Physical) or LTSSM.
• Experience with Clock Domain Crossing (CDC), timing closure, or synthesis flows.