ASIC Design Verification Manager, Google Cloud

• Guide the functional verification team for portions of TPU designs, setting and communicating individual and team priorities that support organizational goals, providing regular feedback and coaching, and developing functional verification infrastructure across subchip, subsystem, and fullchip level environments.
• Define and guide advanced verification strategies, including the use of simulation, for bug hunt, formal verification for corner-case bugs and emulation for system validation.
• Partner with front-end design, architecture, and performance teams to help ensure architectural compliance and achievement of performance goals.
• Analyze coverage from various dimensions and develop monitors and checkers for quality assurance.

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
  
• 10 years of experience with verification, SystemVerilog, and UVM.
• 3 years of experience in people management.

Preferred qualifications:

• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
  
• Experience with universal verification methodology (UVM), SystemVerilog, or other scripting languages such as Python, Perl, Shell, Bash, etc.
• Knowledge of general purpose operating systems such as Linux and Android.
  
• Familiarity with ARM Instruction Set Architecture.

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
  
• 10 years of experience with verification, SystemVerilog, and UVM.
• 3 years of experience in people management.