Silicon Circuit Digital Design Engineer, Cloud Silicon

• Simulate and optimize clock tree networks with respect to key clock quality metrics.
• Evaluate clock IPs such as PLLs, FLLs, other adaptive systems involving ADCs, clock drivers, receivers and differential buffers.
• Perform detailed jitter compliance simulations for Serdes, PCIe reference clocks and other high speed clocks.
• Guide sub-system clocking on best practices in terms of clock quality.
• Provide inputs to timing and sign-off teams on clock inputs such as jitter, duty-cycle, and aging margins.

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
• 4 years of experience with mixed-signal analog integrated circuit design, or equivalent practical experience.
• Experience with analog circuits, simulation, clocks, and analog design.

Preferred qualifications:

• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
  

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
• 4 years of experience with mixed-signal analog integrated circuit design, or equivalent practical experience.
• Experience with analog circuits, simulation, clocks, and analog design.