ASIC Power Engineer, ML Accelerators

• Contribute to design power modeling and drive convergence to power goals.
• Investigate, specify, and deploy architectural and microarchitectural power optimization techniques.
• Define best practices and methodologies to achieve low-power designs.
• Collaborate with cross-functional software and system teams to create novel power management architectures to meet power goals.

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
• 8 years of experience in silicon design or architecture (e.g., logic design, power architecture, performance, or SoC design).
• Experience with power design, power modeling, power architecture, or power reduction methodologies/techniques.

Preferred qualifications:

• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
• Experience defining and implementing chip-wide power management architectures and designs.
• Experience in power modeling, measurement, and correlation across the pre- and post-silicon phases.
• Understanding of modern power and thermal management techniques at both the silicon and system levels (including Dynamic Voltage and Frequency Scaling (DVFS), turboing, thermal management, and system-level tradeoffs).
• Ability to solve open-ended power and performance problems under ambiguity.

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
• 8 years of experience in silicon design or architecture (e.g., logic design, power architecture, performance, or SoC design).
• Experience with power design, power modeling, power architecture, or power reduction methodologies/techniques.