Principal / Senior Principal Design Verification Engineer- CXL / PCIe / Ethernet

Principal / Senior Principal Design Verification Engineer – CXL / PCIe / Ethernet:

Role Overview 

We are seeking an experienced Principal / Senior Principal Design Verification Engineer to lead the verification of next-generation connectivity IPs and SoCs powering AI and cloud infrastructure. This is a highly visible technical leadership role where you will define verification strategies, drive methodology improvements, mentor engineering teams, and collaborate across architecture, RTL, firmware, validation, and silicon teams to ensure first-pass silicon success. 

The ideal candidate is passionate about building world-class verification environments, has deep expertise in protocol verification, and enjoys solving complex architectural challenges. 

Key Responsibilities 

Technical Leadership 

• Lead the verification strategy for complex IPs and SoC subsystems from architecture through silicon. 

• Define verification methodologies, reusable verification frameworks, and best practices across multiple programs. 

• Drive verification planning, execution, coverage closure, and sign-off. 

• Identify verification risks early and proactively drive mitigation plans. 

• Lead technical reviews including architecture, RTL, verification, and tape-out readiness reviews. 

Design Verification 

• Architect and develop scalable UVM/System Verilog verification environments. 

• Develop constrained-random, coverage-driven verification methodologies. 

• Design scoreboards, protocol monitors, checkers, assertions (SVA), and functional coverage models. 

• Debug complex RTL, protocol, timing, and integration issues. 

• Drive regression planning, automation, and continuous integration improvements. 

• Develop reusable VIP and verification infrastructure across multiple product lines. 

Protocol Verification 

Lead verification efforts involving one or more of: 

• Compute Express Link (CXL 2.x / 3.x) 

• PCI Express (Gen4/Gen5/Gen6) 

• Ethernet (10G–800G) 

• AXI, APB, AHB 

• High-speed SerDes interfaces 

• Memory interfaces including DDR/LPDDR/HBM (preferred) 

Cross-Functional Collaboration 

• Work closely with Architecture teams to influence design for verification. 

• Partner with RTL designers during implementation and debug. 

• Collaborate with Firmware, Emulation, FPGA, Post-Silicon Validation, and System Engineering teams. 

• Support customer issue analysis and silicon bring-up when required. 

Technical Mentorship 

• Mentor and coach verification engineers across multiple experience levels. 

• Establish verification standards and engineering excellence across the organization. 

• Drive innovation in automation, verification productivity, and quality metrics. 

Required Qualifications 

• Bachelor's or Master's degree in Electrical Engineering, Electronics Engineering, Computer Engineering, or a related field. 

• Minimum10+ years (Principal) or 15+ years (Senior Principal) of experience in Design Verification. 

• Strong expertise in System Verilog and UVM. 

• Extensive experience in verification planning, execution, and sign-off. 

• Deep understanding of constrained-random verification and coverage-driven methodologies. 

• Strong experience with assertions (SVA), functional coverage, and protocol compliance. 

• Excellent debugging skills involving RTL, simulation, protocol analysis, and waveform debugging. 

• Experience with industry-standard simulators such as Synopsys VCS, Cadence Xcelium, or Siemens Questa. 

Preferred Technical Expertise 

Strong experience in several of the following areas: 

• CXL Cache, Memory, and I/O protocols 

• PCIe Transaction, Data Link, and Physical Layers 

• Ethernet MAC/PCS/PMA architecture 

• Coherency protocols 

• High-speed interconnects 

• AI accelerator connectivity 

• Data center SoC architecture 

• Multi-chip and chiplet-based systems 

• Performance verification 

• Low-power verification 

• CDC/RDC verification 

• Formal Verification 

• Portable Stimulus (PSS) 

• Python, Perl, Tcl, or similar scripting languages 

• Emulation and FPGA prototyping 

Leadership Expectations 

• Own technical direction for large verification programs. 

• Influence architecture and product quality through early engagement. 

• Drive cross-functional execution across geographically distributed teams. 

• Establish reusable verification IP and methodology. 

• Mentor engineers and help grow technical capability within the organization. 

• Champion engineering excellence, quality, and continuous improvement. 

Preferred Experience

• Experience leading verification for large SoCs or complex connectivity IPs. 

• Proven success delivering multiple first-pass silicon programs. 

• Experience with AI infrastructure, cloud networking, or hyperscale data center technologies. 

• Familiarity with customer-facing debug and post-silicon issue resolution. 

• Contributions to verification methodology, reusable frameworks, or industry standards are a strong plus. 

Salary range will be is $185,000 to $230,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits.