Junior RTL Design Engineer, Google Cloud

• Define the IP microarchitecture level design document such as interface protocol, block diagram, transaction flow, pipeline, etc.
• Perform RTL development (coding and debug in Verilog, SystemVerilog).
• Conduct function/performance simulation debug and Lint/CDC/FV/UPF checks.
• Engage in synthesis, timing/power closure, and ASIC silicon bring-up.
• Contribute to verification test plan and coverage analysis of block and SoC-level.

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
• 4 years of experience with digital logic design principles, Register-Transfer Level (RTL) design concepts, and languages such as Verilog or System Verilog.
• Experience in logic design and debug with Design Verification (DV).
• Experience with microarchitecture and specifications.

Preferred qualifications:

• Experience with logic synthesis techniques to optimize Register-Transfer Level (RTL) code, performance and power as well as low-power design techniques.
• Experience with design sign off and quality tools (e.g., Lint, CDC, VCLP, etc.).
• Experience in a scripting language like Python or Perl.
• Knowledge of SoC architecture and assertion-based formal verification.
• Knowledge of one of these areas, PCIe, UCIe, DDR, AXI, ARM processors family.
• Knowledge of high performance and low power design techniques.

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
• 4 years of experience with digital logic design principles, Register-Transfer Level (RTL) design concepts, and languages such as Verilog or System Verilog.
• Experience in logic design and debug with Design Verification (DV).
• Experience with microarchitecture and specifications.