Low Power Verification Engineer, Physical Design

• Design, deploy, and carry out post-layout low power verification methodologies according to execution schedules and tapeout signoff criteria to ensure successful multi-voltage implementation.
• Validate the implementation of complex multi-voltage design collateral, performing gate-level checks using industry-standard tools (e.g., Synopsys VCLP) to ensure power/ground integrity and Unified Power Format (UPF) alignment.
• Drive the resolution of complex Physical Design and Place & Route (P&R) anomalies, specifically mitigating issues such as wrong domain buffering, secondary power routing failures, and isolation clamping errors.
• Perform debugging on advanced Clock Tree Synthesis (CTS) implementations, analyzing tool behavior around level shifters in high fanout networks, duty cycle distortions, and multi-voltage skew management.
• Drive the continuous refinement of power state tables (PST) and Unified Power Format (UPF) scripts to ensure accurate translation from Golden RTL to the final physical netlist.

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, or equivalent practical experience.
• 8 years of experience performing post-layout physical netlist validation and low-power signoff within advanced ASIC design workflows.
• Experience with static low-power rule-checking tools (such as VCLP or CLP), including experience in debugging structural checks and signal corruption issues.
• Experience validating special low-power components (isolation cells, power switches, level shifters, retention registers, and always-on cells) across all stages from synthesis to place and route.

Preferred qualifications:

• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
  
• Experience with scripting languages (e.g., Tcl or Python) to automate Engineering Change Orders (ECOs) and improve verification workflows.
• Experience interacting with P&R tools (Innovus, Fusion) and an understanding of standard cell timing, hierarchical construction, and physical logic optimization.
• Experience with UPF implementation, low-power architecture design, and resolving low-power check violations.
• Expertise in resolving technical issues within the IEEE 1801 UPF framework and physical gate-level netlist flow.
• Familiarity with timing-driven Place and Route, including insertion, scaling, level shifters, and always-on cells.

• Bachelor's degree in Electrical Engineering, Computer Engineering, or equivalent practical experience.
• 8 years of experience performing post-layout physical netlist validation and low-power signoff within advanced ASIC design workflows.
• Experience with static low-power rule-checking tools (such as VCLP or CLP), including experience in debugging structural checks and signal corruption issues.
• Experience validating special low-power components (isolation cells, power switches, level shifters, retention registers, and always-on cells) across all stages from synthesis to place and route.