Silicon Micro-architecture Design Lead, Google Cloud

• Lead a team of Engineers in the design organization to deliver complex IPs or Subsystems. Communicate and work with multi-disciplined and multi-site teams.
• Define micro-architecture (uArch) specifications and block-level design documents, including interface protocols, block diagrams, transaction flows, and pipeline details.
• Perform RTL development, subsystem integration, and System on a Chip (SoC) integration, as well as Lint, CDC, FV, and UPF checks.
• Participate in simulation debug, synthesis, timing and power closure, and silicon bring-up.
• Participate in test plan and coverage analysis of the block and SOC-level verification.

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• 10 years of experience in ASIC/SoC development with Verilog/SystemVerilog.
• Experience in micro-architecture and design of IPs and Subsystems.
• Experience in ASIC/SoC design verification, synthesis, timing/power analysis, and Design for Testing (DFT).

Preferred qualifications:

• Master's or PhD degree in Electrical Engineering, Computer Engineering, or Computer Science, with an emphasis on computer architecture.
• Experience with coding languages (e.g., Python or Perl).
• Experience in System on a Chip (SoC) designs and integration flows.
• Knowledge of arithmetic units, bus architectures, processor design, accelerators, or memory hierarchies.
• Knowledge of high-performance and low-power design techniques.

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• 10 years of experience in ASIC/SoC development with Verilog/SystemVerilog.
• Experience in micro-architecture and design of IPs and Subsystems.
• Experience in ASIC/SoC design verification, synthesis, timing/power analysis, and Design for Testing (DFT).