Silicon Physical Design Engineer

• Take end-to-end ownership of synthesis-to-Graphic Data System (GDS) implementation of complex physical partitions/subsystems.
• Collaborate with sign-off teams and own the convergence of Electromigration (EM)/IR, power, timing and physical verification.
• Collaborate with cross-functional teams RTL, DFT, CAD to improve Power/Performance/Area in physical design.
• Use and improve CAD recipes for PPA benefits.

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• 4 years of experience in physical design.
• Experience in high performance synthesis, Place and Route (PnR) and sign-off optimizations. Experience in sign-off convergence, including Static Timing Analysis (STA), electrical checks and physical verification.
• Experience with programming in TCL/Python.

Preferred qualifications:

• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
• Experience with constraints, synthesis or Clock Tree Synthesis (CTS).
• Experience using Machine Learning (ML) in physical design/signoff convergence (e.g., STA/EMIR closure).
• Knowledge of Verilog/SystemVerilog.
• Understanding of circuit design, device physics and deep submicron technology.

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• 4 years of experience in physical design.
• Experience in high performance synthesis, Place and Route (PnR) and sign-off optimizations. Experience in sign-off convergence, including Static Timing Analysis (STA), electrical checks and physical verification.
• Experience with programming in TCL/Python.