Technical Lead Manager, Machine Learning, Memory Subsystem Design

• Lead, mentor and manage a team of RTL Design and DV Engineers developing DRAM subsystems including HBM.
• Collaborate closely with the cross-functional teams (e.g., Design for Test, Signal/Power Integrity, Packaging, Physical Design, Software, Silicon Validation, Silicon Engineering) to plan and execute throughout the development cycle.
• Interface with third party IP providers of memory related IP including controllers, physical layers, and verification models during the selection and implementation phases of projects.
• Interface with DRAM manufacturers during the design and validation of DRAM subsystems.
• Drive improvements in design methodologies, processes, and quality control measures.

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
• 15 years of experience in semiconductor design or design verification.
• 6 years of experience in people management, developing employees.
  
• Experience in designing or verifying DRAM-based memory subsystems.

Preferred qualifications:

• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
  
• Experience in creating and validating HBM-based memory subsystems.

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
• 15 years of experience in semiconductor design or design verification.
• 6 years of experience in people management, developing employees.
  
• Experience in designing or verifying DRAM-based memory subsystems.