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Hardware Design Engineering, Senior Director - Signal Connectivity Rack-Scale Platforms Astera Labs · San Jose, California, United States · Posted 3 months ago

Firmware Engineer Tech Lead Astera Labs · San Jose, California, United States · Posted 6 months ago

Principal Design Verification Engineer- SerDes/PHY IP Astera Labs · San Jose, California, United States · Posted 3 weeks ago Lead functional verification for high-speed SerDes/PHY IP blocks powering AI infrastructure, architecting UVM-based verification environments and driving coverage closure across an...

Physical Design Engineering, VP Astera Labs · San Jose, California, United States · Posted 1 month ago

Firmware Engineer Tech Lead Astera Labs · San Jose, California, United States · Posted 2 months ago

STA Physical Design Engineer, Senior Principal Astera Labs · San Jose, California, United States · Posted 6 months ago

Principal Physical Design Engineer, STA Astera Labs · San Jose, California, United States · Posted 4 months ago

Principal Physical Design Engineer -EMIR & Power Integrity Astera Labs · San Jose, California, United States · Posted 1 month ago

Principal Physical Design Engineer Astera Labs · San Jose, California, United States · Posted 5 months ago

Senior Embedded Software Engineer - Ethernet Retimers Astera Labs · San Jose, California, United States · Posted 3 months ago

Principal / Senior Principal Design Verification Engineer- CXL / PCIe / Ethernet Astera Labs · San Jose, California, United States · Posted 1 week ago Lead verification strategy for next-generation connectivity IPs and SoCs supporting AI and cloud infrastructure, with 10+ years (Principal) or 15+ years (Senior Principal) of desig...

Principal Physical Design Engineer, Methodology Astera Labs · San Jose, California, United States · Posted 1 month ago

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