Physical Design Lead, Static Timing Analysis

• Lead effort for timing constraint creation and validation, timing analysis and timing Engineering Change Order (ECO) creation, and final timing sign-off for complex ASICs.
  
• Drive both static timing analysis methodology development and support, as well as chip implementation and timing signoff execution.
  
• Develop, support and execute implementation flows around industry-standard static timing and parasitic extraction tools.
  
• Interface with the broader team to triage and resolve reported technical issues, escalating complex tool-related problems to Electronic Design Automation (EDA) vendors and deliver timely and effective solutions.
  
• Lead collaboration with RTL design and DFT team for high quality integrations and timing constraints.
  

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
  
• 10 years of experience in static timing analysis (STA), including 5 years of experience in a technical leadership capacity.
• Experience achieving full-chip timing convergence and authoring, reviewing, or validating timing constraints (e.g., Synopsys Design Constraints (SDC)).
• Experience using tool command language (Tcl) commands for timing analysis, timing closure, parasitic extraction, noise glitch, or crosstalk.
• Experience using electronic design automation (EDA) tools (e.g., PrimeTime, Tempus, Timevision, or STAR-RC).
• Experience analyzing cross-chip clock distribution networks.

Preferred qualifications:

• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
  
• 12 years of experience in the domain of static timing analysis and 5 years of experience in leading STA activities for SOC.
• Experience leading physical design or STA flow/methodology to successful tape-outs and shipping silicon.
• Experience analyzing data trends, semiconductor device physics, SPICE simulation, and full-chip static timing topics.
• Exceptional track record of on-time STA sign-off and delivery within physical design execution cycles.
• Drove full-chip timing convergence, timing constraint validation, and complex timing ECO implementation and sign-off.

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
  
• 10 years of experience in static timing analysis (STA), including 5 years of experience in a technical leadership capacity.
• Experience achieving full-chip timing convergence and authoring, reviewing, or validating timing constraints (e.g., Synopsys Design Constraints (SDC)).
• Experience using tool command language (Tcl) commands for timing analysis, timing closure, parasitic extraction, noise glitch, or crosstalk.
• Experience using electronic design automation (EDA) tools (e.g., PrimeTime, Tempus, Timevision, or STAR-RC).
• Experience analyzing cross-chip clock distribution networks.