Silicon Physical Design STA Lead, Google Cloud

• Lead a team of individuals, set and communicate individual and team priorities that support organizational goals. Meet regularly with individuals to discuss performance and development, and provide feedback and coaching. Take ownership of Static Timing Analysis (STA) of one or more physical design partitions and top level.
• Drive to the closure of timing and power consumption of the design.
• Contribute to design methodology, libraries, and code review.
• Define the physical design STA constraints rule sets for the physical design engineers.

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
  
• 10 years of experience with advanced design, including clock/voltage domain crossing, Design for Testing (DFT), and low power designs.
• 6 years of experience in people management, developing employees.
  
• Experience with Static Timing Analysis (STA) convergence on blocks, Subsystem (SS) or SoC.
• Experience with System on a Chip (SoC) cycles.
• Experience in high-performance, high-frequency, and low-power designs.

Preferred qualifications:

• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
  
• Experience with scripting languages such as Perl, Python, or Tcl.
  
• Experience in Very-Large-Scale Integration (VLSI) design in SoC or experience with multiple-cycles of SoC in ASIC design.
• Experience in coding constraints and scripting with TCL.

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
  
• 10 years of experience with advanced design, including clock/voltage domain crossing, Design for Testing (DFT), and low power designs.
• 6 years of experience in people management, developing employees.
  
• Experience with Static Timing Analysis (STA) convergence on blocks, Subsystem (SS) or SoC.
• Experience with System on a Chip (SoC) cycles.
• Experience in high-performance, high-frequency, and low-power designs.