Senior RTL Design Engineer, TPU

• Work separately to create and review management and control subsystem's design microarchitecture specifications.
• Develop SystemVerilog RTL to implement logic for ASIC products according to established coding and quality guidelines.
• Work with architecture and power teams to evaluate features and their impact.
• Work with design validation (DV) teams to create test plans to verify, and debug design RTL.
• Work with physical design teams to ensure design meets physical requirements and timing closure.

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• 8 years of experience in ASIC design.
• Experience with SystemVerilog/RTL coding.
• Experience with scripting languages (e.g., Tcl, Python or Perl).

Preferred qualifications:

• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
• Experience interacting with software, system hardware, and other cross-functional teams.
• Experience with chip management, clocking, reset, and peripherals like I2C, SPI, UART, etc.
• Understanding of digital design fundamentals, including synchronous and asynchronous logic, state machines and bus protocols.

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• 8 years of experience in ASIC design.
• Experience with SystemVerilog/RTL coding.
• Experience with scripting languages (e.g., Tcl, Python or Perl).