ASIC Design Verification Manager, TPU Compute

• Lead the functional verification team for significant portions of TPU Compute team, setting and communicating individual and team priorities that support organizational goals, providing regular feedback and coaching, and developing advanced functional verification infrastructure such as subchip, subsystem, and fullchip level environments.
• Define and drive the execution of comprehensive verification strategies for complex compute subsystems, working with cross-functional design, architecture and power teams to achieve architectural compliance and alignment with performance and power goal.
• Architect scalable, reusable verification environments and flows, driving the adoption of industry-leading methodologies to improve efficiency across the team.
• Provide technical leadership and mentorship to junior engineers, drive code reviews, establish verification quality standards, and guide cross-functional efforts for silicon bring-up.
• Partner with architects and design leads to influence micro-architectural decisions to improve verification throughput and overall quality.

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
  
• 10 years of experience with verification, SystemVerilog, and UVM.
• 3 years of experience in people management.

Preferred qualifications:

• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
  
• 12 years of experience with industry-standard tools, languages, and methodologies relevant to the development and verification of high-performance silicon.
• Experience leading verification efforts of complex SoC projects, involving compute subsystems for AI/ML accelerators.
  
• Experience mentoring junior engineers and establishing verification quality standards with excellent investigative and communication skills.
• Proven record of managing verification planning for SoCs, from architecture definition to silicon bring-up.
• Ability to influence cross-functional teams (architecture, design, power, emulation, software) to optimize verification efficiency and product quality.

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
  
• 10 years of experience with verification, SystemVerilog, and UVM.
• 3 years of experience in people management.