Physical Design Engineer, 3D Technology

• Drive development of a leading edge 3D technology platform for custom, high performance ASIC’s and SoC’s, from design through manufacturing, packaging, and test.
• Optimize digital blocks for performance, power, area, and reliability using physical design and circuit techniques.
• Define optimal methodologies by investigating performance, power, and area across different technology nodes and implementation techniques.
• Work with our physical design, technology, circuits, and architecture teams plus IP partners in advanced CMOS nodes.
• Design and build custom circuits at the transistor and gate levels to support physical design and floorplan optimization.

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
  
• 4 years of experience with physical design and 3D integration technologies, such as 3D-IC, 2.5D, chip stacking, vertical stacking, Integrity, or Through-Silicon Vias (TSV).
• Experience running industry standard tools for chip design, such as Synopsys, Cadence, Siemens EDA/Mentor Graphics.

Preferred qualifications:

• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
  
• Experience with Power, Performance, and Area (PPA) design trade-offs and optimizations in physical design spaces.
• Experience with advanced FinFET and gate-all-around (GAA) technology nodes, including enabling physical design flows in these nodes.
• Experience delivering optimized digital place-and-route blocks leading to product tapeouts.
• Experience with programming/scripting (e.g., TCL, Python, or Perl) for design flow automation.
• Understanding of standard cells, SRAMs, power, noise, and IR analysis.

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
  
• 4 years of experience with physical design and 3D integration technologies, such as 3D-IC, 2.5D, chip stacking, vertical stacking, Integrity, or Through-Silicon Vias (TSV).
• Experience running industry standard tools for chip design, such as Synopsys, Cadence, Siemens EDA/Mentor Graphics.