Senior TPU Design Engineer, Silicon

• Contribute to Machine Learning IPs for Google Silicon SoCs.
• Define microarchitecture details for Machine learning processors and accelerators along with specification of data flows and integration requirements for Subsystem Development.
• Drive RTL development, debug functional/performance simulations.
• Meet schedule commitments and provide strong support to customers.
• Participate in synthesis, timing/power estimation, and Field-programmable Gate Array (FPGA)/silicon bring-up.

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
• 8 years of experience with RTL design using Verilog/System Verilog and microarchitecture.
• 4 years of experience in leading IP/SoC design teams.
• Experience with ARM-based SoCs, interconnects, and ASIC methodology.

Preferred qualifications:

• Master’s degree in Electrical/Computer Engineering, or a related field.
• 10 years of experience with IP design for Complex IPs in Machine learning, Neural Processors, Multimedia or GPUs.
• Experience with methodologies for low power estimation, timing closure, and synthesis.
• Experience leading technical teams.

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
• 8 years of experience with RTL design using Verilog/System Verilog and microarchitecture.
• 4 years of experience in leading IP/SoC design teams.
• Experience with ARM-based SoCs, interconnects, and ASIC methodology.